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NS32FX211 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # NS32FX211
Description  Microprocessor Compatible Real Time C
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

NS32FX211 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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AC Switching Characteristics
READ TIMING DATA FROM PERIPHERAL TO MICROPROCESSOR
VDD e 5V g5% CL e 100 pF
Symbol
Parameter
Commercial Specification
Units
TA e 0 Cto a75 C
Min
Typ
Max
tAD
Address Bus Valid to Data Valid
390
650
ns
tCSD
Chip Select On to Data Valid
140
300
ns
tRD
Read Strobe On to Data Valid
140
300
ns
tRW
Read Strobe Width (Note 3 Note 7)
300
DC
ns
tRA
Address Bus Hold Time from Trailing
0ns
Edge of Read Strobe
tCSH
Chip Select Hold Time from Trailing
0ns
Edge of Read Strobe
tRH
Data Hold Time from Trailing
70
160
ns
Edge of Read Strobe
tHZ
Time from Trailing Edge of Read Strobe
250
ns
Unitl OP Drivers are TRI-STATE
WRITE TIMING DATA FROM MICROPROCESSOR TO PERIPHERAL
VDD e 5V g5%
Symbol
Parameter
Commercial Specification
Units
TA e 0 Cto a70 C
Min
Typ
Max
tAW
Address Bus Valid to Write Strobe
O
400
125
ns
(Note 4 Note 6)
tCSW
Chip Select On to Write Strobe
O
250
100
ns
tDW
Data Bus Valid to Write Strobe
O
400
220
ns
tWW
Write Strobe Width (Note 6)
250
95
ns
tWCS
Chip Select Hold Time Following
0ns
Write Strobe
O
tWA
Address Bus Hold Time Following
0ns
Write Strobe
O
tWD
Data Bus Hold Time Following
100
35
ns
Write Strobe
O
tAWS
Address Bus Valid before
70
20
ns
Start or Write Strobe
Note 3
Except for special case restriction with interrupts programmed max read strobe width of control register (ADDR 0) is 30 ms See section on Interrupt
Programming
Note 4
All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR)
Note 5
Input test waveform peak voltages are 24V and 04V Output signals are measured to their 24V and 04V levels
Note 6
Write stobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low ie WS e CS a WR Hence write
strobe commences when both signals are low and terminates when the first signal returns high
Note 7
Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low ie RS e CS a RD
Note 8
Typical numbers are at VCC e 50V and TA e 25 C
3


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