Electronic Components Datasheet Search |
|
ST24E64EB1TR Datasheet(PDF) 11 Page - STMicroelectronics |
|
ST24E64EB1TR Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 16 page BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN WC PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 WC DATA IN 2 AI01120 PAGE WRITE (cont’d) WC (cont’d) DATA IN N ACK ACK ACK NO ACK R/W ACK ACK ACK NO ACK R/W NO ACK NO ACK Figure 9. Write Modes Sequence with Write Control = 1 sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte out- put, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automat- ically incremented after each byte output. After a count of the last memory address, the address counter will ’roll-over’ and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the ST24/25E64 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25E64 terminate the data transfer and switch to a standby state. 11/16 ST24E64, ST25E64 |
Similar Part No. - ST24E64EB1TR |
|
Similar Description - ST24E64EB1TR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |