Electronic Components Datasheet Search |
|
ADC121S625 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
|
|
ADC121S625 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 20 page ADC121S625 Converter Electrical Characteristics (Note 8) (Continued) The following specifications apply for V A = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 to 3.2 MHz, fIN = 20 kHz, CL = 100 pF, un- less otherwise noted. Boldface limits apply for T A =TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 7) POWER SUPPLY CHARACTERISTICS PSRR Power Supply Rejection Ratio Offset Change with 1.0V change in V A 71 dB Gain Error Change with 1.0V change in V A 83 dB AC ELECTRICAL CHARACTERISTICS f SCLK Maximum Clock Frequency 4.8 3.2 MHz (min) f SCLK Minimum Clock Frequency 200 800 kHz (max) f S Maximum Sample Rate 300 200 ksps (min) t ACQ Track/Hold Acquisition Time 1.5 SCLK cycles (min) 2.0 SCLK cycles (max) t CONV Conversion Time 12 12 SCLK cycles t CYC Throughput Time Normal Operation 16 SCLK cycles Short Cycled 14 SCLK cycles (min) f RATE Throughput Rate 200 ksps (max) t AD Aperture Delay 6 ns ADC121S625 Timing Specifications (Note 8) The following specifications apply for V A = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 MHz to 3.2 MHz, CL = 100 pF, Boldface limits apply for T A =TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits Units t CFCS SCLK Fall toCS Fall 0 ns (min) t CSCR CS Fall to SCLK Rise (Note 9) 0 ns (min) t CHLD SCLK Fall to Data Change Hold Time (Note 9) 10 ns (min) t CDV SCLK Fall to Next D OUT Valid 38 100 ns (max) t DIS Rising Edge of CS To D OUT Disabled 38 50 ns (max) t EN 2nd SCLK Fall after CS Fall to D OUT Enabled 6 50 ns (max) t CH SCLK High Time 42 60 ns (min) t CL SCLK Low Time 42 60 ns (min) t r D OUT Rise Time 5 50 ns (max) t f D OUT Fall Time 13 50 ns (max) Note 1: Absolute maximum ratings are limiting values which indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance ( θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC121S625 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO ohms. Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: Clock should be in low when CS is asserted, as indicated by the tCSCR and tCFCS specifications. Note 10: While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate being slower than fSCLK/16. www.national.com 5 |
Similar Part No. - ADC121S625 |
|
Similar Description - ADC121S625 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |