TMP90C041A datasheet(8/12 Pages) TOSHIBA

Part #	TMP90C041A

Description	CMOS 8-Bit Microcontrollers

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Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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TMP90C041A

• AC output level High 2.2V/Low 0.8V

• AC input level High 2.4V/Low 0.45V (D0 – D7)

High 0.8VCC/Low 0.2VCC (excluding D0 – D7)

4.3 AC Characteristics

TA = -20 ~ 70

°C V

CC = 5V ± 10%

CL = 50pF

Symbol

Parameter

Variable

10MHz Clock

16MHz Clock

Unit

Min

Max

Min

Max

Min

Max

tOSC

OSC. Period = x

80

1000

100

–

82.5

–

ns

tCYC

CLK Period

4x

400

–

250

–

ns

tWL

CLK Low width

2x - 40

–

160

–

85

–

ns

tWH

CLK High width

2x - 40

–

160

–

85

–

ns

tAC

Address Setup to RD, WR

x - 45

–

55

–

17

–

ns

tRR

RD Low width

2.5x - 40

–

210

–

115

–

ns

tCA

Address Hold Time After RD, WR

0.5x - 30

–

20

–

5

–

ns

tAD

Address to Valid Data In

–

3.5x - 95

–

255

–

124

ns

tRD

RD to Valid Data In

–

2.5x - 80

–

170

–

77

ns

tHR

Input Data Hold After RD

0

–

0–0–

ns

tWW

WR Low width

2.5x - 40

–

210

–

115

–

ns

tDW

Data Setup to WR

2x - 50

–

150

–

75

–

ns

tWD

Data Hold After WR

20

70

20

70

20

70

ns

tCWA

RD, WR to Valid WAIT

–

1.5x - 80

–

70

–

14

ns

tAWA

Address to Valid WAIT

–

2.5x - 130

–

120

–

27

ns

tWAS

WAIT Setup to CLK

50

–

50

–

50

–

ns

tWAH

WAIT Hold After CLK

0

–

0–0–

ns

tRV

RD/WR Recovery Time

1.5x - 35

–

115

–

58

–

ns

tCPW

CLK to Port Data Output

–

x + 200

–

300

–

263

ns

tPRC

Port Data Setup to CLK

200

–

200

–

200

–

ns

tCPR

Port Data Hold After CLK

100

–

100

–

100

–

ns

tCHCL

RD/WR Hold After CLK

x - 60

–

40

–

10

–

ns

tCLC

RD/WR Setup to CLK

1.5x - 25

–

125

–

68

–

ns

tCLHA

Address Hold After CLK

1.5x - 80

–

70

–

13

–

ns

tACL

Address Setup to CLK

2.5x - 80

–

170

–

76

–

ns

tCLD

Data Setup to CLK

x - 50

–

50

–

12

–

ns

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