EM39LV800

8M Bits (512Kx16) Flash Memory

SPECIFICATION

This specification is subject to change without further notice. (04.09.2004 V1.0)

Page 7 of 25

Hardware Data Protection

Noise/Glitch Protection:

A WE# or CE# pulse of less than 5 ns will not initiate a

write cycle.

1.5V.

Write Inhibit Mode:

Forcing OE# Low, CE# High, or WE# High will inhibit the

Write operation. This prevents inadvertent write during

power-up or power-down.

Software Data Protection (SDP)

The EM39LV800 provides the JEDEC approved Software Data Protection (SDP) scheme for

Program and Erase operations. Any Program operation requires the inclusion of the

three-byte sequence. The three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent Write operations, especially during

the system power-up or power-down transition. Any Erase operation requires the inclusion of

six-byte sequence. See Table 3 for the specific software command codes. During SDP

sequence.

Common Flash Memory Interface (CFI)

The EM39LV800 contains the CFI information to describe the characteristics of the device.

In order to enter the CFI Query mode, the system must write three-byte sequence, same as

Software ID Entry command, with 98H (CFI Query command) to address 5555H in the last

byte sequence. Once the device enters the CFI Query mode, the system can read CFI data

at the addresses given in Tables 4 through 6. The system must write the CFI Exit command

to return to Read mode from the CFI Query mode.