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M28W320FSU70ZA6T Datasheet(PDF) 9 Page - STMicroelectronics |
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M28W320FSU70ZA6T Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 49 page  9/49 M28W320FSU, M28W640FSU SIGNAL DESCRIPTIONS See Figures 2 and 3, Logic Diagrams and Table 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs. The Address Inputs select the cells in the memory array to access during Bus Read operations. Address Inputs range from A0 to A20 for the M28W320FSU. The M28W640FSU has an additional A21 address line. During Bus Write operations they control the commands sent to the Command Interface of the internal state ma- chine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write En- able, W, whichever occurs first. Reset (RP). The Reset input provides a hard- ware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is mini- mized. After Reset all blocks are in the Locked state. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range ap- plied to the pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 en- ables these functions (see Table 12., DC Charac- teristics, for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on Program or Erase. If VPP is set to VPPH, it acts as a power supply pin. In this condition VPP must be stable until the Pro- gram/Erase algorithm is completed (see Table 14. and Table 15.). A Quadruple Word Program com- mand will be ignored if VPP is not set to VPPH while a Double Word Program can be performed even if VPP is set to VDD. VSS Ground. VSS is the reference for all voltage measurements. Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1µF ca- pacitor close to the pin. See Figure 8., AC Mea- surement Load Circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents. |
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