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K4H560438D

DDR SDRAM

Rev. 2.2 Mar. ’03

Notes 1. Includes

≤ 3nH.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

DDR SDRAM IDD spec table

AC Operating Conditions

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.31

V

3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

VIL(AC)

VREF - 0.31

V

3

Input Differential Voltage, CK and CK inputs

VID(AC)

0.7

VDDQ+0.6

V

1

Input Crossing Point Voltage, CK and CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu

lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Parameter

Specification

Address &

Control pins

Data pins

Maximum peak amplitude allowed for overshoot

1.6 V

1.2V

Maximum peak amplitude allowed for undershoot

1.6 V

1.2V

The area between the overshoot signal and VDD must be less than or equal to

4.5 V-ns

2.5 V-ns

The area between the undershoot signal and GND must be less than or equal to

4.5 V-ns

2.5 V-ns

Overshoot/Undershoot specification

Symbol

64Mx4

Unit

Notes

K4H560438D-GC(L)B3

(DDR333)

K4H560438D-GC(L)A2,B0

(DDR266A/B)

IDD0

90

80

mA

IDD1

110

100

mA

IDD2P

3

3

mA

IDD2F

25

20

mA

IDD2Q

20

18

mA

IDD3P

35

30

mA

IDD3N

55

45

mA

IDD4R

150

120

mA

IDD4W

160

135

mA

IDD5

180

165

mA

IDD6

Normal

3

3

mA

Low power

1.5

1.5

mA

Optional

IDD7A

290

250

mA