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SP8855D Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc |
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SP8855D Datasheet(HTML) 7 Page - Zarlink Semiconductor Inc |
7 / 14 page SP8855D 7 Pin 40 Pin 41 Current Multiplication Factor 0 0 1.0 0 1 1.5 1 0 2.5 1 1 4.0 Table 1 Pin 19 current ] Vcc * 1.6V R set I pin 19(mA) multiplication factor 2 p mA radian Phase detector gain + To allow for control direction changes introduced by the design of the PLL, pin 23 can be programmed to reverse the control direction of the loop by transposing the Fpd and Fref connections. In order that any external phase detector will also be reversed by this function, the Fpd and Fref outputs are also interchanged as shown in Table 2. Output for RF Phase Lag Control direction pin 23 Pin 20 1 Current Source 0 Current Sink Table 2 The Fpd and Fref signals to the phase detector are available on pin 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. When the Fpd/Fref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 W may be used connected to ground to reduce the fall time of the output pulse. The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pumps output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pull up resistor is used in place of the LED. A small capacitor connected from the C–lock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. The phase detector can be disabled by pulling pin 39 to logic low. REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION TEN BIT REFERENCE COUNTER 29 28 27 26 25 24 23 22 21 20 PIN 29 28 27 26 25 24 23 22 21 20 PHASE DETECTOR GAIN CONTROL M COUNTER 3 BIT A COUNTER 213 210 211 212 RF DIVIDER PROGRAMMING PIN ALLOCATION Fig. 6 Programming data format 29 30 31 32 33 34 35 36 37 38 PIN 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 see Table 1 |
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