Philips Semiconductors

NE56610/11/12 Series

System Reset

February 23, 2001

8 of 9

document number here

Test Circuits

Figure 16. Test Circuit 1

Figure 17. Test Circuit 2

2

1

5

4

GND

SUB

M/R

3

10

V1

/ 10V

A2

A1

V2

A - DC Ammeter

V = DC Voltmeter

2

1

5

4

GND

SUB

M/R

3

10

/ 10V

CL = 100pF

CRT = Oscilliscope

CRT

5.0 V

Input

Pulse

VS typ -0.4V

+0.4V

0V

VS typ

Input Pulse

Application Information

When the manual reset is not needed, the M/R, manual reset

pin is connected to ground as shown in Figure 16 - Typical Hard

Reset Circuit. A capacitor connected from VCC to ground is

recommended when the VCC supply impedance is appreciably

high. This may be the situation with a poor quality or aged

battery.

Figure 16. Typical Hard Reset Circuit

The second example, shown in Figure 17 - Manual Reset

Circuit, incorporates a manual reset switch from the M/R pin to

VCC. When the manual switch is closed, VOUT reset is logic

high. Conversely, when it is opened, VOUT reset is logic low. As

a precaution a clamp diode is placed from the M/R pin to ground

to insure that the pin does not go below - 0.3V.

Figure 17. Manual Reset Circuit

23

1

54

GND

SUB

M/R

To CPU

Reset Pin

23

1

54

GND

SUB

M/R

To CPU

Reset Pin

Clamp

Manual

Switch

Diode