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UPD8880 Datasheet(PDF) 7 Page - NEC |
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UPD8880 Datasheet(HTML) 7 Page - NEC |
7 / 24 page Data Sheet S16032EJ3V0DS 7 µ PD8880 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Pin name Pin No. Min. Typ. Max. Unit Shift register clock pin capacitance 1 Cφ 1 φ 1 4 − 1100 − pF 13 − 1100 − pF φ 1 total capacitance − 2200 − pF Shift register clock pin capacitance 2 Cφ 2 φ 2 5 − 1100 − pF 20 − 1100 − pF φ 2 total capacitance − 2200 − pF Last stage shift register clock pin capacitance 1 Cφ 1L φ 1L 14 − 70 − pF Last stage shift register clock pin capacitance 2 Cφ 2L φ 2L 19 − 70 − pF Reset gate clock pin capacitance Cφ RB φ RB 2 − 20 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 3 − 20 − pF Transfer gate clock pin capacitance φ TG1 18 − 200 − pF φ TG2 17 − 200 − pF Cφ TG φ TG3 15 − 200 − pF Remarks 1. Pins 4 and 13 ( φ 1), 5 and 20 (φ 2) are each connected inside of the device. 2. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and φ 2. |
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