µPD485505

5

Data Sheet M10059EJ7V0DS00

2. Operation Mode

µPD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).

For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).

2.1 Write Cycle

When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock

input.

The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-

line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.

When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which

at this time.

Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin

incrementing again.

2.2 Read Cycle

When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input

When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which

this time.

2.3 Write Reset Cycle/Read Reset Cycle

After power up, the

µPD485505 requires the initialization of internal circuits because the read and write

address pointers are not defined at that time.

It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and

RCK, and then input the RSTW and RSTR signals to initialize the circuit.

Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write

Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.

Remark

Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.