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MOS INTEGRATED CIRCUIT

FLOW THROUGH OPERATION

Document No. M15958EJ5V0DS00 (5th edition)

Date Published April 2005 NS CP(K)

Printed in Japan

DATA SHEET

The mark

shows major revised points.

2002, 2005

Description

The

static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and

output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input

(CLK).

The

speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The

for high density and low capacitive loading.

Features

• Synchronous operation

• 100 percent bus utilization

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for flow through operation

• All registers triggered off positive clock edge

• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 7.5 ns (117 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4 (

/BW1 and /BW2 (

• Three chip enables for easy depth expansion

• Common I/O using three state outputs