Preliminary Data Sheet M17506EJ1V1DS

8

CONTENTS

1. Initialization ................................................................................................................................................ 10

2. Partial Refresh ........................................................................................................................................... 11

2. 1 Standby Mode......................................................................................................................................................... 11

2. 2 Density Switching ................................................................................................................................................... 11

2. 3 Standby Mode Status Transition............................................................................................................................. 11

2. 4 Addresses for Which Partial Refresh Is Supported................................................................................................. 12

3. Burst Operation ......................................................................................................................................... 13

3. 1 Features of Burst Operation ................................................................................................................................... 13

3. 2 Latency ................................................................................................................................................................... 13

3. 3 Burst Length, Burst Sequence, Wrap Around......................................................................................................... 16

3. 4 Burst Read End ...................................................................................................................................................... 17

3. 5 Burst Write End ...................................................................................................................................................... 18

3. 6 Burst Read Termination.......................................................................................................................................... 19

3. 7 Burst Write Termination .......................................................................................................................................... 20

3. 8 /WAIT signal behavior............................................................................................................................................. 21

3. 9 /WAIT output........................................................................................................................................................... 21

4. Mode Register Settings............................................................................................................................. 23

4. 1 Mode Register Setting Method ............................................................................................................................... 23

4. 1. 1

Cautions for Setting Mode Register............................................................................................................. 23

4. 1. 2

Mode Register Setting/Reading................................................................................................................... 25

4. 1. 3

Partial refresh Density ................................................................................................................................. 25

4. 1. 4

Burst length ................................................................................................................................................. 25

4. 1. 5

Function mode............................................................................................................................................. 26

4. 1. 6

Driver strength............................................................................................................................................. 26

4. 1. 7

Read Latency .............................................................................................................................................. 26

4. 1. 8

Single Write ................................................................................................................................................. 26

4. 1. 9

Valid Clock Edge ......................................................................................................................................... 26

4. 1. 10

Reset to Asynchronous.............................................................................................................................. 26

4. 1. 11

/WE control................................................................................................................................................ 26

4. 1. 12

Setting of unused bits ................................................................................................................................ 26

4. 2 Mode Register Reading .......................................................................................................................................... 27

4. 2. 1

Cautions for Setting Mode Register............................................................................................................. 27

4. 2. 2

Data read from mode register...................................................................................................................... 27

5. Address, /OE, /WE, DM control ................................................................................................................ 29

5. 1 Relation of address inputs and /OE control ............................................................................................................ 29

5. 2 Address Latching .................................................................................................................................................... 30

5. 3 Read / Write Command Loading............................................................................................................................. 32

5. 4 /OE control during burst read operation.................................................................................................................. 34

5. 4. 1

/OE HIGH to LOW during burst read operation ........................................................................................... 34

5. 4. 2

/OE LOW to HIGH during burst read operation ........................................................................................... 35

5. 5 Write data mask signal (DM) control....................................................................................................................... 36

5. 5. 1

Controlling write data mask signal (DM) in write cycle................................................................................. 36

5. 5. 2

Write data mask (DM) truth table................................................................................................................. 37