 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD46128512F9-CR2 Datasheet(PDF) 6 Page - NEC |
|
||||||||||||||||||||||||||||||
UPD46128512F9-CR2 Datasheet(HTML) 6 Page - NEC |
|
|
6 / 82 page  Preliminary Data Sheet M17507EJ2V0DS 6 μ PD46128512-X Burst Operation Mode /CE1 CE2 CLK /ADV /OE /WE /LB /UB DQ /WAIT DQ0 to DQ7 DQ8 to DQ15 Note8 Not selected (Standby Mode 1) H H × × × × × × High-Z High-Z High-Z Not selected (Standby Mode 2) Note1 × L × × × × × × High-Z High-Z High-Z Start address latch L H Note4 L × Note7 × Note7 × Note9 × Note9 High-Z Note5 High-Z Note5 × Advanced burst read to next address H L H DOUT DOUT Output Note4 Valid Burst read suspend Note2 H High-Z High-Z HIGH Burst read resume Note2 L DOUT DOUT HIGH Burst read termination Note3 × × High-Z High-Z High-Z Advanced burst write to next address L H L DIN DIN Output Note4 Valid Burst write suspend Note2 H High-Z High-Z HIGH Burst write resume Note2 L DIN DIN HIGH Burst write termination Note3 × × High-Z High-Z High-Z Abort write Note6 L × × Note10 HIGH HIGH High-Z High-Z HIGH Notes 1. CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition). 2. Be sure to suspend or resume a burst read after outputting the first read access data. Be sure to suspend or resume a burst write after latching the first write data. Burst write suspend or resume is available when setting WC = 1 (/WE level control) through Mode Register Set. 3. /CE1 must be fixed HIGH during tTRB specification until next read or write operation. 4. Valid clock edge shall be set either positive or negative edge through Mode Register Set. 5. If /OE = LOW and /LB = /UB = LOW, output is valid. If /OE = LOW and /LB = /UB = HIGH, output is high impedance. If /WE = LOW, output is high impedance. If /OE = /WE = HIGH, output is high impedance. 6. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not available. 7. Both of two pins (/OE and /WE) or either of two should be connected to HIGH. It is prohibited to bring the both /OE and /WE to LOW. 8. Refer to the 4.10 /WAIT. 9. For the Burst Read, the /UB, /LB setup time to CLK (tBC) must be satisfied. For the Burst Write, the /UB, /LB setup time to CLK (tBC) must be satisfied. Once /LB and /UB inputs are determined, they must not be changed until the end of burst operation. 10. In case of WC = 0, /WE is HIGH. In case of WC = 1, /WE is LOW. The explanation of WC refers to Table 5-2. Mode Register Definition (5th Bus Cycle) and 5.9 /WE control. Remark H, HIGH : VIH, L, LOW : VIL, ×: VIH or VIL, : valid edge |
Similar Part No. - UPD46128512F9-CR2 |
|
Similar Description - UPD46128512F9-CR2 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
