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UPD44324364F5-E50-EQ2 Datasheet(PDF) 9 Page - NEC |
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UPD44324364F5-E50-EQ2 Datasheet(HTML) 9 Page - NEC |
9 / 32 page 9 Preliminary Data Sheet M16781EJ1V0DS µPD44324084, 44324094, 44324184, 44324364 Power-on Sequence The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable. 1. Clock starts after VDD/VDDQ stable VDD/VDDQ VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Clock Start 1,024 cycles or more Stable Clock Start Normal Operation Clock 2. Clock starts before VDD/VDDQ stable VDD/VDDQ VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Clock Start 1,024 cycles or more Stable Clock 30 ns (MIN.) DLL Reset or DLL Off Start Normal Operation Clock |
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