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MOS INTEGRATED CIRCUIT

4-WORD BURST OPERATION

Document No. M16784EJ1V0DS00 (1st edition)

Date Published October 2004 NS CP(K)

Printed in Japan

PRELIMINARY DATA SHEET

2003

Description

The

2,097,152-word by 18-bit and the

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive

edge of K and /K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

• 1.8 ± 0.1 V power supply and HSTL I/O

• DLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability with

• User programmable impedance output

• Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan