IW4015BN datasheet(4/5 Pages) INTEGRAL

Part #	IW4015BN

Description	Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS

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Manufacturer	INTEGRAL [Integral Corp.]

Direct Link	http://www.iksemi.com/

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IW4015B

27

AC ELECTRICAL CHARACTERISTICS(C

L=50pF, RL=200kΩ, Input tr=tf=20 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

≥-55°C25°C

≤125°C

Unit

tmax

Maximum Clock Frequency (Figure 1)

5.0

10

15

3

6

8.5

3

6

8.5

1.5

3

4.25

MHz

tPHL, tPLH

Maximum Propagation Delay, Clock to Q

(Figure 1)

5.0

10

15

320

160

120

320

160

120

640

320

240

ns

tPHL

Maximum Propagation Delay, Reset to Q

(Figure 2)

5.0

10

15

400

200

160

400

200

160

800

400

320

ns

tTHL, tTLH

Maximum Output Transition Time, Any Output

(Figure 1)

5.0

10

15

200

100

80

200

100

80

400

200

160

ns

CIN

Maximum Input Capacitance

-

7.5

pF

TIMING REQUIREMENTS(C

L=50pF, RL=200 kΩ, Input tr=tf=20 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

≥-55°C25°C

≤125°C

Unit

tw

Minimum Pulse Width, Clock (Figure 1)

5.0

10

15

180

80

50

180

80

50

360

160

100

ns

tw

Minimum Pulse Width, Reset (Figure 2)

5.0

10

15

200

80

60

200

80

60

400

160

120

ns

tsu

Minimum Setup Time, Data to Clock

(Figure 3)

5.0

10

15

70

40

30

70

40

30

140

80

60

ns

th

Minimum Hold Time, Clock to Data

(Figure 3)

5.0

10

15

0

ns

tr, tf

Maximum Input Rise and Fall Time (Figure 1)

5.0

10

15

6

2

15

6

2

30

12

4

µs

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