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MT88L70AN Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc |
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MT88L70AN Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc |
11 / 16 page MT88L70 Data Sheet 11 Zarlink Semiconductor Inc. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. *NOTES: 1. Used for guard-time calculation purposes only and tested at -4 dBm. 2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high. AC Electrical Characteristics - VDD = 3.0 V+20%/-10%, VSS =0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 6. Characteristics Sym. Min. Typ.‡ Max. Units Conditions 1 T I M I N G Tone present detect time tDP 511 14 ms Note 1 2 Tone absent detect time tDA 0.548.5 ms Note 1 3 Tone duration accept tREC 40 ms Note 2 4 Tone duration reject tREC 20 ms Note 2 5 Interdigit pause accept tID 40 ms Note 2 6 Interdigit pause reject tDO 20 ms Note 2 7 O U T P U T S Propagation delay (St to Q) tPQ 11 µsTOE=VDD 8 Propagation delay (St to StD) tPStD 20 µs TOE=VDD 9 Output data set up (Q to StD) tQStD 5.0 µs TOE=VDD 10 Propagation delay (TOE to Q ENABLE) tPTE 50 ns load of 10 k Ω, 50 pF 11 Propagation delay (TOE to Q DISABLE) tPTD 130 ns load of 10 k Ω, 50 pF 12 P D W N Power-up time tPU 30 ms Note 3 13 Power-down time tPD 20 ms 14 C L O C K Crystal/clock frequency fC 3.5759 3.5795 3.5831 MHz 15 Clock input rise time tLHCL 110 ns Ext. clock 16 Clock input fall time tHLCL 110 ns Ext. clock 17 Clock input duty cycle DCCL 40 50 60 % Ext. clock 18 Capacitive load (OSC2) CLO 15 pF |
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