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ATU18_352 Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATU18_352 Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 12 page 8 4318C–ULC–08/05 ATU18 PLL Applications ATMEL PLL is configurable to support applications as: - Clock tree delay reduction - Zero delay buffer - Phase shift - Frequency synthesis Clock Tree Delay Reduction Typically, clock tree synthesis is able to build a very performant clock tree (for example: 0.15ns of skew for a clock tree connected to 25000 Flipflops). For that, however, the clock tree latency is increased during clock tree insertion. To satisfy Tco propagation delay, the PLL can be used to reduce and even remove the clock tree delay. Frequency Synthesis By adding dividers on input clock and feedback clock, the PLL can be used to multiply the input frequency by a factor determined by the user, as illustrated below: Figure 3. PLL Frequency Synthesis For example, with a 32Mhz input clock, to generate a 160 Mhz frequency clock on the output outx0, it is necessary to set the input clock divider M to 1 and the feed-back clock divider N to 10. VCO Charge Pump Phase comp %M CLKin freqin %N %2 outx0 CLKout PLL divout |
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