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MB86291A Datasheet(PDF) 6 Page - Fujitsu Component Limited. |
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MB86291A Datasheet(HTML) 6 Page - Fujitsu Component Limited. |
6 / 25 page MB86291A 6 Notes : • The host interface transfers data signals at a fixed width of 32 bits. • There are 23 lines for address signals handled in double words ( = 32 bits) and 32 Mbytes of address space. • The external bus can be used at an operating frequency of 100 MHz maximum. • The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output. • The host interface supports DMA transfer using an external DMA controller. • The host interface generates a host processor interrupt signal. • The RESET pin requires low level input of at least 300 µs after setting “S” (PLL reset signal) to high level. • Fix the TEST signal at high level. • In the V832 mode, connect the following pins as specified : •••• Vide Output Interface Notes : • The video output interface contains an 8-bit D/A converter to output analog RGB signals. Also, the eight-bit RGB digital output pins can connect an external digital video encoder. • Using an additional external circuit, the video output interface can generate composite video signals. • The video output interface can provide display synchronized with external video. The mode for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set dot clock as for normal display. SCARLET Pin Name V832 Signal Name A24 MWR DTACK TC DRACK DMAAK Pin Name Input/output Function DCLKO Output Display dot clock signal output DCLKI Input Dot clock signal input HSYNC Input/output Horizontal sync signal output Horizontal sync signal input in external synchronization mode VSYNC Input/output Vertical sync signal output Vertical sync signal input in external synchronization mode CSYNC Output Composite sync signal output EO Input Even/odd-number field identification input GV Output Graphics/video select signal R0-R7 Output Digital video (R) signal output G0-G7 Output Digital video (G) signal output B0-B7 Output Digital video (B) signal output AOUTR Analog output Analog video (R) signal output AOUTG Analog output Analog video (G) signal output AOUTB Analog output Analog video (B) signal output VREF Analog Reference voltage input pin ACOMPR Analog R-signal compensation pin ACOMPG Analog G-signal compensation pin ACOMPB Analog B-signal compensation pin VRO Analog Reference current setting pin |
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