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CAT24FC65WE-TE13 Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT24FC65WE-TE13 Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 10 page CAT24FC65/66 6 Doc. No. 1047, Rev. H © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24FC65/66. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24FC65/66 acknowledges once more and the Master generates the STOP condi- tion. At this time, the device begins an internal program- ming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24FC65/66 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 63 additional bytes. After each byte has been transmitted, CAT24FC65/66 will respond with an acknowledge, and internally increment the six low order address bits by one. The high order bits remain un- changed. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24FC65/66 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24FC65/66 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issu- ing the start condition followed by the slave address for a write operation. If CAT24FC65/66 is still busy with the write operation, no ACK will be returned. If CAT24FC65/66 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT24FC65/66 will accept both slave and byte addresses, but the memory location accessed is protected from program- ming by the device’s failure to send an acknowledge after the first byte of data is received. Figure 7. Page Write Timing Figure 6. Byte Write Timing *=Don't Care Bit *=Don't Care Bit A15–A8 SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS A C K *** A15–A8 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS DATA n+63 DATA A C K S T O P A C K DATA n A C K P A C K *** |
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