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PTH12060LAZT Datasheet(PDF) 5 Page - Texas Instruments |
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PTH12060LAZT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 29 page  www.ti.com ELECTRICAL CHARACTERISTICS PTH12060W/L SLTS217D–MAY 2003–REVISED OCTOBER 2005 TA = 25°C; VI =12V;VO = 1.8 V; CI = 560 µF, CO =0µF, and IO =IOmax (unless otherwise stated) PTH12060L UNIT PARAMETER TEST CONDITIONS MIN TYP MAX Over ∆Vadj range 85°C, 200 LFM airflow 0 10(1) IO Output current A 25°C, natural convention 0 10(1) VI Input voltage range Over IO range 10.8 13.2 V VOtol Set-point voltage tolerance ±2(2) %VO ∆Regtemp Temperature variation –40°C<TA <85°C ±0.5 %VO ∆Regline Line regulation Over VI range ±10 mV ∆Regload Load regulation Over IO range ±12 mV ∆Regtot Total output variation Includes set-point, line, load, –40°C ≤ TA ≤ 85°C ±3%VO ∆Vadj Output voltage adjust range Over VI range 0.8 1.8 V RSET = 130 Ω,VO = 1.8 V 88% RSET =3.57kΩ,VO = 1.5 V 87% η Efficiency IO =8A RSET = 12.1 kΩ,VO = 1.2 V 84% RSET = 32.4 kΩ,VO = 1 V 82% RSET = open circuit, VO = 0.8 V 81% VO >1V 20(3) 20-MHz bandwidth, VO ripple (peak-to-peak) mVPP with CO2 = 10 µF ceramic VO ≤ 1V 30(3) IO trip Overcurrent threshold Reset, followed by auto-recovery 20 A ttr 1 A/µs load step, 50 to 100% Recovery time 70 µS Transient response IOmax, VO over/undershoot 100 mV ∆Vtr CO1 = 330 µF VOadj Margin up/dow adjust ±5% IILmargin Margin input current (pins 9/10) Pin to GND –8(4) µA IILtrack Track input current (pin 8) Pin to GND –0.11(5) mA dVtrack/dt Track slew rate capability CO ≤ CO (max) 1V/ms VI increasing 9.5 10.4 UVLO Under-voltage lockout V VI decreasing 8.8 9 Inhibit Control (pin 3) Referenced to GND VIH Input high voltage VI – 0.5 Open(5) V VIL Input low voltage –0.2 0.5 IIL inhibit Input low current Pin to GND 0.24 mA II inhibit Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA f s Switching frequency Over VI and IO ranges 200 250 300 kHz CI External input capacitance 560(6) µF Nonceramic 0 330(7) 5500(8) Capacitance value µF CO External output capacitance Ceramic 0 300 Equivalent series resistance (nonceramic) 4(9) mΩ Per Bellcore TR-332 6.4 MTBF Reliability 106 Hr 50% stress, TA =40°C, ground benign (1) See SOA curves or consult factory for appropriate derating. (2) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1% with 100 ppm/°C or better temperature stability. (3) The peak-to-peak output ripple voltage is measured with an external 10-µF ceramic capacitor. See the standard application schematic. (4) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc. (5) This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 8). If it is left open-circuit, the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. For further information, see the application information section. (6) A 560-µF input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms of ripple current. (7) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the transient response. (8) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a voltage supervisor, CO(max) is reduced to 2200 µF. See the application notes for further guidance. (9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 mΩ as the minimum when using max-ESR values to calculate. 5 |
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