AT61162E-PM40M-E datasheet(10/14 Pages) ATMEL

10 / 14 page

10

AT61162E

4157D–AERO–06/04

Figure 3. Write Cycle 3. CS1 or CS2 Controlled

Note:

The internal write time of the memory is defined by the overlap of CS

1 Low and CS2

HIGH and WE LOW. Both signals must be activated to initiate a write and either signal

can terminate a write by going in actived. The data input setup and hold timing should be

referenced to the activated edge of the signal that terminates the write. Data out is high

impedance if OE = VIH.

Figure 4. Read Cycle nb 1

Figure 5. Read Cycle nb 2

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