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HPC36400EV Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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HPC36400EV Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 30 page Timing Waveforms (Continued) Serial Decoder Timing Diagram (Modes 5 67) TLDD10422 – 16 Symbol Parameter Min Max Comments Units TPFS Number of HCK1 Periods between FS Rising Edges 34 TAFS Number of HCK1 Falling Edges during FS High 1 32 TEFS Hold of FS Low after HCK1 Falling Edge 10 Early FS ns TLFS Setup of FS Rising Edge before HCK1 Falling Edge 45 Late FS (Note 8) ns TVFC Delay of TX Output Valid after HCK1 Rising Edge 60 (Note 7) ns THFS Hold of FS High after HCK1 Falling Edge 20 ns TSFS Setup of FS Falling Edge before HCK1 Rising Edge 20 ns TTTC Delay of TX output TRI-STATE after HCK1 Rising Edge 40 ns Note 7 This spec is for 1st bit only Remaining bits are spec’d by transmitter TVTC spec Note 8 Receiver specs TVRS and TVRH are required along with TLFS for receiver operation using serial decoder 9 |
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