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5962F0052101QXC Datasheet(PDF) 2 Page - Intersil Corporation |
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5962F0052101QXC Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 2 page 2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Die Characteristics DIE DIMENSIONS: 3559 µm x 4420µm (129 mils x 174 mils) Thickness: 483 µm ± 25.4µm (19 mils ± 1 mil) INTERFACE MATERIALS Glassivation Type: Phosphorus Silicon Glass (PSG) Thickness: 8.0kÅ ± 1.0kÅ Top Metallization Type: AlSiCu Thickness: 16.0kÅ ± 2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 222 Metallization Mask Layout IS-1715ARH NOTES: 1. All double sized pads should be double bonded. 2. All pin 2 and pin 10 VCC pads are bonded to VCC for power and noise considerations. (These are lead-frame connected in packaged devices.) VCC (10) VSS (13) INPUT (14) T1 (15) ENBL (16) VCC (2) PWR (3) VSS (4) VCC (2) (10) VCC (12) VSS (11) T2 (10) VCC (6) AUX (5) VSS (2) VCC IS-1715ARH |
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