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AM93LC86ITSA Datasheet(PDF) 5 Page - Anachip Corp |
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AM93LC86ITSA Datasheet(HTML) 5 Page - Anachip Corp |
5 / 12 page AM93LC86 16384-bits Serial Electrically Erasable PROM (Preliminary) Anachip Corp. www.anachip.com.tw Rev 0.1 Oct 20, 2003 5/12 Functional Description Erase/write enable (EWEN) Before any device programming (WRITE, WRAL, ERASE, and ERAL) can be done, the EWEN instruction must be executed first. When Vcc is applied, this device powers up in the EWDS state. The device then remains in a erase/write disable (EWDS) state until a EWEN instruction is executed. Thereafter the device remains enabled until a EWDS instruction is executed or until Vcc is removed. (shown in Figure 4) Note: Neither the EWEN nor the EWDS instruction has any effect on the READ instruction. Erase/write disable (EWDS) The erase/write disable (EWDS) instruction disables all programming capabilities. This protects the entire part against accidental modification of data until a EWEN instruction is executed. (When Vcc is applied, this part powers up in the EWDS state.) To protect data, a EWDS instruction should be executed upon completion of each programming operation. Note: Neither the EWEN nor the EWDS instruction has any effect on the READ instruction. (shown in figure 5) Write (WRITE) The WRITE instruction includes 8-bit or 16-bit of data to be written into the specified register. After the last data bit has been applied to DI, and before the next rising edge of SK, CS must be brought low. The falling edge of CS initiates the self-timed programming cycle. After a minimum wait of 250ns (5V operation) from the falling edge of CS (tcs), DO will indicate the READY/BUSY status of the chip if CS is brought HIGH. This means that logical "0" implies the programming is still in progress while logical "1" indicates the selected register has been written, and the part is ready for another instruction. (shown in figure 6) Note: The combination of CS HIGH, DI HIGH and the rising edge of the SK clock, resets the READY/BUSY flag. Therefore, it is important if you want to access the READY/BUSY flag, not to reset it through this combination of control signals. Before a WRITE instruction can be executed, the device must be in the Write enable (WEN) state. Write all (WRAL) The Write All (WRAL) instruction programs all registers with the data pattern specified in the instruction. While the WRAL instruction is being loaded, the address field becomes a sequence of DON'T-CARE bits. (Shown in Figure 7) As with the WRITE instruction, if CS is brought HIGH after a minimum wait of 250ns (tcs), the DO pin indicates the READY/BUSY status of the chip. (shown in figure 7) Erase (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after minimum of tcs, will cause DO to indicate the READ/BUSY status of the chip. To explain this, a logical "0" indicates the programming is still in progress while a logical "1" indicates the erase cycle is complete and the part is ready for another instruction. (shown in figure 8) Erase all (ERAL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1". (shown in figure 9) |
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