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A43E16161V-75F Datasheet(PDF) 10 Page - AMIC Technology |
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A43E16161V-75F Datasheet(HTML) 10 Page - AMIC Technology |
10 / 46 page A43E16161 PRELIMINARY (August, 2005, Version 0.0) 9 AMIC Technology, Corp. Mode Register Filed Table to Program Modes Register Programmed with MRS Address BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function 0 RFU W.B.L TM CAS Latency BT Burst Length (Note 3) (Note 1) (Note 2) Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 0 0 1 - 1 Interleave 0 0 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1 Vendor Use Only 0 1 1 3 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved 0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 512(Full) Reserved Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle. 2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled. 3. BA must be 0,0 to select the Mode Register (vs. the Extended Mode Register). Extended Mode Register Table BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 All have to be set to “0” Bank Up/Down DS 0 PASR (Note) Driver Strength Partial-Array Self Refresh: Driver Strength A6 A5 Driver Strength A7 A2 A1 A0 Banks to be Self-Refreshed 0 0 Full 0 0 0 0 All banks (Bank 0, 1) 0 1 3/4 0 0 0 1 Reserved 1 0 1/2 0 0 1 0 Bank 0 1 1 1/4 0 0 1 1 Reserved 0 1 X X Reserved 1 0 0 0 All banks (Bank 0, 1) 1 0 0 1 Reserved 1 0 1 0 One bank (Bank 1) 1 0 1 1 Reserved 1 1 X X Reserved Note: BA must be 1 to select the Extended Mode Register (vs. the Mode Register) |
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