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A29L160ATG-90F Datasheet(PDF) 2 Page - AMIC Technology |
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A29L160ATG-90F Datasheet(HTML) 2 Page - AMIC Technology |
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2 / 42 page  A29L160A Series 2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory (May, 2005, Version 0.1) 1 AMIC Technology, Corp. Features Single power supply operation - Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors Access times: - 70/90 (max.) Current: - 9 mA typical active read current - 20 mA typical program/erase current - 200 nA typical CMOS standby - 200 nA Automatic Sleep Mode current Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequence Top or bottom boot block configurations available Embedded Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies data at specified addresses Typical 100,000 program/erase cycles per sector 20-year data retention at 125 °C - Reliable operation for the life of the system CFI (Common Flash Interface) compliant - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Compatible with JEDEC-standards - Pinout and software compatible with single-power-supply Flash memory standard - Superior inadvertent write protection Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations Ready / BUSY pin (RY / BY ) - Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP) Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation Hardware reset pin ( RESET ) - Hardware method to reset the device to reading array data Package options - 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA General Description The A29L160A is a 16Mbit, 3.3 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160A is offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160A can also be programmed in standard EPROM programmers. The A29L160A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160A also offers the ability to program in the Erase Suspend mode. The standard A29L160A offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable ( OE ) controls. The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29L160A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. |
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