A43P26161V-95UF datasheet(8/44 Pages) AMICC

Part #	A43P26161V-95UF

Description	1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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A43P26161

PRELIMINARY

(July, 2005, Version 1.1)

7

AMIC Technology, Corp.

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol

Parameter

-75

-95

Unit

Note

tRRD(min)

Row active to row active delay

2

CLK

1

tRCD(min)

RAS to

CAS delay

19

24

ns

1

tRP(min)

Row precharge time

19

24

ns

1

tRAS(min)

45

60

ns

1

tRAS(max)

Row active time

100

µs

tRC(min)

Row cycle time

64

84

ns

1

tCDL(min)

Last data in new col. Address delay

7.5

9.5

ns

2

tRDL(min)

Last data in row precharge

2

CLK

1, 2

tBDL(min)

Last data in to burst stop

7.5

9.5

ns

2

tCCD(min)

Col. Address to col. Address delay

7.5

9.5

ns

Note:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

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