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MC100EL34 Datasheet(PDF) 1 Page - ON Semiconductor

Part # MC100EL34
Description  첨2,첨4,첨8 Clock Generation Chip
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EL34 Datasheet(HTML) 1 Page - ON Semiconductor

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 2
© Motorola, Inc. 1996
12/93
÷2, ÷4, ÷8 Clock
Generation Chip
The MC10/100EL34 is a low skew
÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the VBB output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPS
™ Data Book DL140/D). If a single-ended input is to be used, the
VBB output should be connected to the CLK input and bypassed to ground
via a 0.01
µF capacitor. The VBB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
75kΩ Internal Input Pulldown Resistors
>1000V ESD Protection
VCC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0
Q1
VCC
Q2
15
16
14
13
12
11
10
2
1
3
4
5
6
7
VCC
9
8
Q2
Q0
EN
NC
CLK
CLK
VBB
MR
VEE
D
Q
R
Q
R
÷2
Q
R
÷4
Q
R
÷8
Q1
MC10EL34
MC100EL34
PIN
FUNCTION
CLK
Diff Clock Inputs
EN
Sync Enable
MR
Master Reset
VBB
Reference Output
Q0
Diff
÷2 Outputs
Q1
Diff
÷4 Outputs
Q2
Diff
÷8 Outputs
PIN DESCRIPTION
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
FUNCTION
Divide
Hold Q0–3
Reset Q0–3
FUNCTION TABLE
Z = Low-to-High Transition
ZZ = High-to-Low Transition
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
1
16


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