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MC100EL34DR2 Datasheet(PDF) 2 Page - ON Semiconductor |
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MC100EL34DR2 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 3 page MC10EL34 MC100EL34 MOTOROLA ECLinPS and ECLinPS Lite DL140 — Rev 3 3–2 AC/DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40 °C 0 °C 25 °C 85 °C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit fMAX Max Toggle Frequency 1100 1100 1100 1100 MHz IEE Power Supply 10EL Current 100EL 39 39 39 39 39 39 39 42 mA VBB Output Reference 10EL Voltage 100EL –1.43 –1.38 –1.30 –1.26 –1.38 –1.38 –1.27 –1.26 –1.35 –1.38 –1.25 –1.26 –1.31 –1.38 –1.19 –1.26 V IIH Input High Current 150 150 150 150 µΑ tPLH tPHL Propagation CLK →Q0 Delay to CLK →Q1,2 Output MR →Q 960 900 750 1200 1140 1060 960 900 750 1200 1140 1060 960 900 750 1200 1140 1060 970 910 790 1210 1150 1090 ps tSKEW Within-Device Skew 100 100 100 100 ps tS Setup Time EN 400 400 400 400 ps tH Hold Time EN 250 250 250 250 ps VPP Minimum Input Swing CLK 250 250 250 250 mV VCMR Common Mode Range CLK –2.0 –0.4 –2.0 –0.4 –2.0 –0.4 –2.0 –0.4 V tr tf Output Rise/Fall Times Q (20% – 80%) 275 525 275 525 275 525 275 525 ps Figure 1. Timing Diagram CLK Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. Internal Clock Disabled Internal Clock Enabled |
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