LH28F640SP datasheet(6/45 Pages) SHARP

Part #	LH28F640SP

Description	64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory

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Manufacturer	SHARP [Sharp Corporation]

Direct Link	http://sharp-world.com/

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LHF64P01

4

Table 1. Pin Descriptions

Symbol

Type

Name and Function

A0

INPUT

ADDRESS INPUTS: Lowest address input in byte mode (BYTE#=VIL : ×8 bit).

Address is internally latched during an erase or a program cycle. This pin is not used in

word mode (BYTE#=VIH : ×16 bit)

A22-A1

INPUT

ADDRESS INPUTS: Inputs for addresses during read, erase and program operations.

Addresses are internally latched during an erase or a program cycle.

DQ15-DQ0

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User

Interface) write cycles, outputs data during memory array, status register, query code,

identifier code reads. Data pins float to high-impedance (High Z) when the chip or

outputs are deselected. Data is internally latched during an erase or program cycle.

DQ15-DQ8 pins are not used in byte mode (BYTE#=VIL : ×8 bit).

CE0,

CE1,

CE2

INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense

amplifiers. When the device is de-selected, power consumption reduces to standby

levels. Refer to Table 2 to determine whether the device is selected or de-selected

depending on the state of CE0, CE1 and CE2.

RP#

INPUT

RESET: When low (VIL), RP# resets internal automation and inhibits erase and program

operations, which provides data protection. RP#-high (VIH) enables normal operation.

After power-up or reset mode, the device is automatically set to read array mode.

RP# must be low during power-up/down.

OE#

INPUT

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE#

INPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of

WE# (whichever occurs first).

STS

OPEN DRAIN

OUTPUT

STATUS: Indicates the status of the internal WSM (Write State Machine). When

configured in level mode (default mode), STS acts as a RY/BY# pin (STS is VOL when

the WSM is executing internal erase or program algorithms). When configured in one of

its pulse modes, STS can pulse to indicate erase/program completion. Refer to Table 9

for STS configuration.

BYTE#

INPUT

BYTE ENABLE: BYTE# VIL places the device in byte mode (×8). In this mode, DQ15-

DQ8 is floated (High Z) and A0 is the lowest address input. BYTE# VIH places the

device in word mode (

×16) and A

1 is the lowest address input.

VPEN

INPUT

MONITORING POWER SUPPLY VOLTAGE: VPEN is not used for power supply pin.

With VPEN≤VPENLK, block erase, (page buffer) program, block lock configuration and

OTP program cannot be executed and should not be attempted.

VCC

SUPPLY

DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the

flash memory are inhibited. Device operations at invalid VCC voltage (refer to DC

Characteristics) produce spurious results and should not be attempted.

VCCQ

SUPPLY

INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output

pins.

GND

SUPPLY

GROUND: Do not float any ground pins.

NC

NO CONNECT: Lead is not internally connected; it may be driven or floated.

Rev. 0.06

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