LP62S16256F-I Series

Preliminary

256K X 16 BIT LOW VOLTAGE CMOS SRAM

PRELIMINARY

(August, 2004, Version 0.4)

1

AMIC Technology, Corp.

Features

Operating voltage: 2.7V to 3.6V

Access times: 55ns / 70ns (max.)

Current:

Very low power version: Operating: 40mA (max.)

Standby:

10

µA (max.)

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Data retention voltage: 2.0V (min.)

Available in 44-pin TSOP and 48-ball CSP (6 × 8mm)

packages

General Description

The LP62S16256F-I is a low operating current 4,194,304-bit

static random access memory organized as 262,144 words by

16 bits and operates on low power voltage from 2.7V to 3.6V.

It is built using AMIC's high performance CMOS process.

Inputs and three-state outputs are TTL compatible and allow

for direct interfacing with common system bus structures.

The chip enable input is provided for POWER-DOWN, device

enable. Two byte enable inputs and an output enable input are

included for easy interfacing.

Data retention is guaranteed at a power supply voltage as low

as 2.0V.

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

Standby

Operating

Package

Type

LP62S16256F-I

-40

°C ~ +85°C

2.7V~3.6V

55ns / 70ns

0.08

µA

0.3

µA

5mA

44L TSOP

48B CSP

°C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configurations

TSOP

CSP (Chip Size Package)

48-pin Top View

GND

VCC

NC

A8

NC

A9

A12

A10

A11

NC

A13

A14

A15

GND

VCC

A0

A3

A5

A6

A4

A1

A2

NC

6

5

4

3

2

1

A

B

C

D

E

F

G

H

A17

NC

A7

A16

LB

HB

WE

OE

CE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A3

A2

A1

A0

CE

VCC

GND

WE

A17

A16

A15

A14

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A11

A10

A9

A8

NC

VCC

GND

LB

HB

OE

A7

A6

A13

A5

A4

A12