6

FN8147.0

March 17, 2005

Notes: 1. INL, DNL, Offset Error and Full Scale error measured at Vbuf with VFB connected to Vbuf.

5. Guaranteed by characterization, not 100% tested.

SYMBOL TABLE

Power-on reset threshold voltage

1.5

2.8

V

RDY indicator minimum voltage

2.6

2.8

V

See figure 1.

RDY indicator delay

100

6000

µs

2k

Ω and 100pF between Vcc and

Address

VH2

VH1

VH0

VL2

VL1

VL0

Count 8

Count 10

3Ch

1

0

1

0

0

1

X

X

X = don’t care

Parameter

Minimum endurance

100,000

Data changes per bit

Data retention

10

Years

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions / Notes

FIGURE 1. RDY PIN TIMING

0V

Device

Ready

Power-down

Device Disabled

Time

Time

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

OE

Vbuf OUTPUT ENABLE TIMING

X79000, X79001, X79002