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X98017 Datasheet(PDF) 5 Page - Intersil Corporation |
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X98017 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 29 page  5 FN8218.0 June 6, 2005 tSETUP DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 1) 1.3 ns tHOLD DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 1) 2.0 ns AC TIMING CHARACTERISTICS (2 WIRE INTERFACE) fSCL SCL Clock Frequency 0 400 kHz Maximum width of a glitch on SCL that will be suppressed 2 XTAL periods min 80 ns tAA SCL LOW to SDA Data Out Valid 5 XTAL periods plus SDA’s RC time constant See comment µs tBUF Time the bus must be free before a new transmission can start 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0ns tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 4 XTAL periods min 160 ns NOTES: 1. Setup and hold times are at a 140MHz DATACLK rate. Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, pixel rate = 170MHz, fXTAL = 25MHz, TA = 25°C, unless otherwise noted (Continued) SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT tSU:STO tDH tHIGH tSU:ST tHD:STA tHD:DAT tSU:DAT SCL SDA IN SDA OUT tF tLOW tBUF tAA tR FIGURE 1. 2 WIRE INTERFACE TIMING DATACLK tSETUP tHOLD DATACLK Pixel Data FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING X98017 |
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