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LP3875EMP-ADJ Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LP3875EMP-ADJ Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 15 page  Application Hints (Continued) Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X when going from 25˚C down to −40˚C. It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP387X. Derating must be applied to the manufacturer’s ESR specification, since it is typically only valid at room temperature. Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating tempera- ture where ESR is maximum. PCB LAYOUT Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the input, output, and ground pins of the LP387X using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out C IN and COUT near the device with short traces to the V IN,VOUT, and ground pins. The regulator ground pin should be connected to the exter- nal circuit ground so that the regulator and its capacitors have a "single point ground". It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and it’s capacitors fixed the problem. Since high current flows through the traces going into V IN and coming from V OUT, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. RFI/EMI SUSCEPTIBILITY RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit’s perfor- mance because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high fre- quency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC regulator. If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass ca- pacitors must be used at the input pin of the IC. If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. The means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the output capacitor(s). In applications where the load is switching at high speed, the output of the IC may need RF isolation from the load. It is recommended that some inductance be placed between the output capacitor and the load, and good RF bypass capaci- tors be placed directly across the load. PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from "clean" circuits where pos- sible, and grounded through a separate path. At MHz fre- quencies, ground planes begin to look inductive and RFI/ EMI can cause ground bounce across the ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. OUTPUT NOISE Noise is specified in two ways- Spot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a spe- cific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of fre- quency. Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/ √Hz or nV/√Hz and total output noise is measured in µV(rms). The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low frequency component and a high frequency component, which depend strongly on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). Using an optimized trade-off of ground pin current and die size, LP3875-ADJ achieves low noise performance and low quiescent current operation. The total output noise specification for LP3875-ADJ is pre- sented in the Electrical Characteristics table. The Output noise density at different frequencies is represented by a curve under typical performance characteristics. SHORT-CIRCUIT PROTECTION The LP3875-ADJ is short circuit protected and in the event of a peak over-current condition, the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on thermal information for power dissipation calculations. SHUTDOWN OPERATION A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively terminated through a 10k Ω pull-up resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. www.national.com 10 |
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