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PM39F010-55PCE Datasheet(PDF) 8 Page - PMC-Sierra, Inc |
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PM39F010-55PCE Datasheet(HTML) 8 Page - PMC-Sierra, Inc |
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8 / 23 page  Programmable Microelectronics Corp. Issue Date: March, 2004, Rev: 1.3 PMC Pm39F010 / Pm39F020 / Pm39F040 8 DEVICE OPERATION (CONTINUED) CHIP ERASE The entire memory array can be erased through a chip erase operation. Pre-programs the devices are not required prior to a chip erase operation. Chip erase starts immediately after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The devices will return to standby mode after the completion of chip erase. SECTOR AND BLOCK ERASE The memory array of Pm39F010/020/040 are organized into uniform 4 Kbyte sectors. A sector erase operation allows to erase any individual sector without affecting the data in others. The memory array of those devices are also organized into uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). A block erase operation allows to erase any individual block. The sector or block erase operation is similar to chip erase. I/O7 DATA# POLLING The Pm39F010/020/040 provide a Data# Polling feature to indicate the progress or completion of a program and erase cycles. During a program cycle, an attempt to read the devices will result in the complement of the last loaded data on I/O7. Once the program operation is com- pleted, the true data of the last loaded data is valid on all outputs. During a sector, block, or chip erase cycle, an attempt to read the device will result a “0” on I/O7. After the erase operation is completed, an attempt to read the device will result a “1” on I/O7. I/O6 TOGGLE BIT The Pm39F010/020/040 also provide a Toggle Bit fea- ture to detect the progress or completion of a program and erase cycles. During a program or erase cycle, an attempt to read data from the device will result a tog- gling between “1” and “0” on I/O6. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase cycle. HARDWARE DATA PROTECTION Hardware data protection protects the devices from un- intentional erase or program operation. It is performed in the following ways: (a) VCC sense: if VCC is below 3.8 V (typical), the write operation is inhibited. (b) Write inhibit: holding any of the signal OE# low, CE# high, or WE# high inhibits a write cycle. (c) Noise filter: pulses of less than 5 ns (typical) on the WE# or CE# input will not initiate a write operation. n o i t a c i f i t n e d I t c u d o r Pa t a D D I r e r u t c a f u n a Mh D 9 : D I e c i v e D 0 1 0 F 9 3 m Ph C 1 0 2 0 F 9 3 m Ph D 4 0 4 0 F 9 3 m Ph E 4 Table 1. Product Identification |
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