MARCH 2001

3.3 VOLT HIGH DENSITY CMOS

SUPERSYNC FIFO™

262,144 x 9

524,288 x 9

IDT72V2101

IDT72V2111

DSC-4669/2

 2001 Integrated Device Technology, Inc.

The SuperSync FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

.EATURES:

IDT72V2101











262,144 x 9

IDT72V2111











524,288 x 9

72V291 SuperSync FIFOs

default to one of two preselected offsets

Through timing (using

OR and IR flags)

simultaneously)

DESCRIPTION:

The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS

First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These

FIFOs offer numerous improvements over previous SuperSync FIFOs,

including the following:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed and short.

• The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is now fixed and short. (The variable

clock cycle counting delay associated with the latency period found on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

SuperSync FIFOs are particularly appropriate for network, video, telecommu-

nications,datacommunicationsandotherapplicationsthatneedtobufferlarge

amountsofdata.

.UNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

262,144 x 9

524,288 x 9

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

HF

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

LD

MRS

REN

RCLK

OE

OFFSET REGISTER

PRS

FWFT/SI

SEN

RT

4669 drw 01