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IDT72V2111L10PFI Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V2111L10PFI Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 27 page  2 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9 PIN CON.IGURATIONS TQFP (PN64-1, order code: PF) TOP VIEW DESCRIPTION (CONTINUED) NOTES: 1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open. 2. This pin may either be tied to ground or left open. 3. DNC = Do Not Connect. TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable ( WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable ( REN)input. DataisreadfromtheFIFOoneveryrisingedge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs. The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating RENandenablinga risingRCLKedge,willshiftthewordfrominternalmemorytothedataoutputlines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FFfunctionsareselectedinIDTStandardmode. TheIRandORfunctionsare selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PIN 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 WEN SEN DC(1) VCC VCC GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) D8 D7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DNC(3) DNC(3) GND DNC(3) DNC(3) VCC DNC(3) DNC(3) DNC(3) GND DNC(3) DNC(3) Q8 Q7 Q6 GND 4669 drw 02 |
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