IDT72V211115PFI datasheet(6/27 Pages) IDT

Part #	IDT72V211115PFI

Description	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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6

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS

SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 3.3V ± 0.15V, TA = 0

°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commercial

Com’l & Ind’l(1)

Commercial

IDT72V2101L10

IDT72V2101L15

IDT72V2101L20

IDT72V2111L10

IDT72V2111L15

IDT72V2111L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fS

Clock Cycle Frequency

—

100

—

66.7

—

50

MHz

tA

Data Access Time

2

6.5

2

10

2

12

ns

tCLK

Clock Cycle Time

10

—

15

—

20

—

ns

tCLKH

Clock High Time

4.5

—

6

—

8

—

ns

tCLKL

Clock Low Time

4.5

—

6

—

8

—

ns

tDS

DataSetupTime

3

—

4

—

5

—

ns

tDH

Data Hold Time

0.5

—

1

—

1

—

ns

tENS

Enable Setup Time

3

—

4

—

5

—

ns

tENH

Enable Hold Time

0.5

—

1

—

1

—

ns

tLDS

LoadSetupTime

3

—

4

—

5

—

ns

tLDH

Load Hold Time

0.5

—

1

—

1

—

ns

tRS

Reset Pulse Width(3)

10

—

15

—

20

—

ns

tRSS

ResetSetupTime

15

—

15

—

20

—

ns

tRSR

Reset Recovery Time

10

—

15

—

20

—

ns

tRSF

Reset to Flag and Output Time

—

10

—

15

—

20

ns

tFWFT

Mode Select Time

0

—

0

—

0

—

ns

tRTS

RetransmitSetupTime

3

—

4

—

5

—

ns

tOLZ

Output Enable to Output in Low Z(4)

0—

0

—

ns

tOE

Output Enable to Output Valid

2

6

2

8

2

10

ns

tOHZ

Output Enable to Output in High Z(4)

26

282

10

ns

tWFF

Write Clock to

FF or IR

—

6.5

—

10

—

12

ns

tREF

Read Clock to

EF or OR

—

6.5

—

10

—

12

ns

tPAF

Write Clock to

PAF

—

6.5

—

10

—

12

ns

tPAE

Read Clock to

PAE

—

6.5

—

10

—

12

ns

tHF

Clock to

HF

—16

—

20

—

22

ns

tSKEW1

Skew time between RCLK and WCLK

8

—

9

—

10

—

ns

for

EF/OR and FF/IR

tSKEW2

Skew time between RCLK and WCLK

12

—

14

—

15

—

ns

for

PAE and PAF

NOTES:

1. Industrial temperature range product for the 15ns speed grade is available as a standard device.

2. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 2

AC TEST CONDITIONS

Figure 2. Output Load

* Includes jig and scope capacitances.

4669 drw 04

330

Ω

30pF*

510

Ω

3.3V

D.U.T.

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