IDT72V3643L15PF datasheet(8/28 Pages) IDT

Part #	IDT72V3643L15PF

Description	3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING 256 x 36, 512 x 36, 1,024 x 36

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING

256 x 36, 512 x 36, 1,024 x 36

COMMERCIAL TEMPERATURERANGE

IDT72V3623L10(1) IDT72V3623L15

IDT72V3633L10(1) IDT72V3633L15

IDT72V3643L10(1) IDT72V3643L15

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

fS

Clock Frequency, CLKA or CLKB

—

100

—

66.7

MHz

tCLK

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA

↑ and B0-B35 before CLKB↑

3—

4

—

ns

tENS1

Setup Time,

CSA, before CLKA

↑; CSB,beforeCLKB↑

4

—

4.5

—

ns

tENS2

Setup Time, ENA, W/

RA and MBA before CLKA

↑; ENB, W/RB and MBB

3

—

4.5

—

ns

before CLKB

↑

tRSTS

Setup Time,

RS1 or PRS LOW before CLKA

↑ or CLKB↑(2)

5—

5

—

ns

tFSS

Setup Time, FS0 and FS1 before

RS1 HIGH

7.5

—

7.5

—

ns

tBES

Setup Time, BE/

FWFT before RS1 HIGH

7.5

—

7.5

—

ns

tSPMS

Setup Time,

SPM before RS1 HIGH

7.5

—

7.5

—

ns

tSDS

Setup Time, FS0/SD before CLKA

↑

3—

4

—

ns

tSENS

Setup Time, FS1/

SEN before CLKA

↑

3—

4

—

ns

tFWS

Setup Time, FWFT before CLKA

↑

0—

0

—

ns

tDH

Hold Time, A0-A35 after CLKA

↑and B0-B35 after CLKB↑

0.5

—

1

—

ns

tENH

Hold Time,

CSA, W/RA, ENA, and MBA after CLKA

↑; CSB, W/RB, ENB, and

0.5

—

1

—

ns

MBB after CLKB

↑

tRSTH

Hold Time,

RS1 or PRS LOW after CLKA

↑ or CLKB↑(2)

4—

4

—

ns

tFSH

Hold Time, FS0 and FS1 after

RS1 HIGH

2

—

2

—

ns

tBEH

Hold Time, BE/

FWFT after RS1 HIGH

2

—

2

—

ns

tSPMH

Hold Time,

SPM after RS1 HIGH

2

—

2

—

ns

tSDH

Hold Time, FS0/SD after CLKA

↑

0.5

—

1

—

ns

tSENH

Hold Time, FS1/

SEN HIGH after CLKA

↑

0.5

—

1

—

ns

tSPH

Hold Time, FS1/

SEN HIGH after RS1 HIGH

2

—

2

—

ns

tSKEW1(3)

Skew Time between CLKA

↑ and CLKB↑ for EF/OR and FF/IR

7.5

—

7.5

—

ns

tSKEW2(3,4)

Skew Time between CLKA

↑ and CLKB↑ for AE and AF

12

—

12

—

ns

NOTES:

1. For 10ns speed grade only: Vcc = 3.3V +/-0.15V, TA = 0

° to +70°C; JEDEC JESD8-A compliant.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

5. Industrial temperature range is available by special order.

TIMING REQUIREMENTS OVER RECOMMENDED RANGES O. SUPPLY

VOLTAGE AND OPERATING .REE-AIR TEMPERATURE

Commercial: Vcc=3.3V± 0.30V; for 10ns (100 MHz) operation, Vcc=3.3V ±0.15V; TA = 0

°C to +70°C; JEDEC JESD8-A compliant

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