1

PS8385B

08/03/00

Product Features

• 10 MHz to 140 MHz operating range

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multiple configurations, see “Available PI6C2308A

Configurations” table

• Input to output delay, less than 150ps

• Multiple low skew outputs

- Output-output skew less than 200ps

- Device-device skew less than 500ps

- Two banks of four outputs, Hi-Z by two select inputs

• Low Jitter, less than 200ps

• 3.3Voperation

• Available in industrial &commercial temperatures

• Packages:

-Space-saving16-pin,150-milSOIC(W)

-16-pinTSSOP(L)

FunctionalDescription

Providingtwobanksof fouroutputs,thePI6C2308Aisa 3.3Vzero-

delay buffer designed to distribute clock signals in applications

includingPC,workstation,datacom,telecom,andhigh-performance

systems. Each bank of four outputs can be controlled by the select

inputs as shown in the Select Input Decoding Table.

The PI6C2308A provides 8 copies of a clock signal that has 150ps

phase error compared to a reference clock. The skew between the

output clock signals for PI6C2308A is less than 200ps. When there

are no rising edges on the REF input, the PI6C2308A enters a power

downstate.Inthismode,thePLLisoffandalloutputsare Hi-Z.This

resultsinlessthan12µAofcurrentdraw.TheSelectInputDecoding

table shows additional examples when the PLL shuts down. The

PI6C2308A configuration table shows all available devices.

The base part, PI6C2308A-1, provides output clocks in sync with

areferenceclock. Withfasterriseandfalltimes,thePI6C2308A-1H

is the high-drive version of the PI6C2308A-1. Depending on which

output drives the feedback pin, PI6C2308A-2 provides 2X and 1X

clocksignalsoneachoutputbank.ThePI6C2308A-3allowstheuser

to obtain 4X and 2X frequencies on the outputs. ThePI6C2308A-4

provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4)

allowsbankBtobeHi-Zwhenalloutputclocksarenotrequired.The

PI6C2308A-6 allows bank B to switch from Reference clock to half

of the frequency of Reference clock using the control inputs S1 and

S2 if Bank A is connected to feedback FBK. In addition, using the

control inputs S1 and S2, the PI6C2308A-6 allows bank A to switch

fromReferenceclockto2XthefrequencyofReferenceclockifBank

B is connected to feedback FBK. For testing purposes, the select

inputs connect the input clock directly to outputs.

Block Diagrams

PinConfigurationPI6C2308A(-1,-1H,-2,-3,-4,-6)

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3.3V Zero-Delay Buffer

PI6C2308A

1

2

3

VDD

4

GND

5

CLKA2

6

CLKB2

7

S1

8

CLKB1

FBK

CLKA3

VDD

CLKB4

CLKB3

S2

16

15

14

13

12

11

10

9

REF

CLKA1

GND

CLKA4

16-Pin

W,L

PLL

MUX

REF

S2

S1

Select Input

Decoding

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB2

CLKB3

CLKB4

CLKB1

PI6C2308A-6

MUX

÷2

÷2

PLL

MUX

Extra Divider (-3, -4)

Extra Divider (-2,-3)

REF

S2

S1

Select Input

Decoding

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB2

CLKB3

CLKB4

CLKB1

PI6C2308A (-1, -1H, -2, -3, -4)

÷2