EBE52UD6ABSA-5C-E datasheet(10/21 Pages) ELPIDA

Part #	EBE52UD6ABSA-5C-E

Description	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)

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Manufacturer	ELPIDA [Elpida Memory]

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EBE52UD6ABSA

Data Sheet E0418E30 (Ver. 3.0)

10

DC Characteristics 1 (TC = 0 to +85

°°°°C, VDD = 1.8V ±±±± 0.1V)

Parameter

Symbol

Grade

max.

Unit

Test condition

Operating current

(ACT-PRE)

(Another rank is in IDD2P)

IDD0

-5C

-4A

660

592

mA

Operating current

(ACT-PRE)

(Another rank is in IDD3N)

IDD0

-5C

-4A

960

860

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE)

(Another rank is in IDD2P)

IDD1

-5C

-4A

720

652

mA

Operating current

(ACT-READ-PRE)

(Another rank is in IDD3N)

IDD1

-5C

-4A

1020

920

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

-5C

80

Precharge power-down

standby current

IDD2P

-4A

64

mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

-5C

200

Precharge quiet standby

current

IDD2Q

-4A

160

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

-5C

240

Idle standby current

IDD2N

-4A

200

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

-5C

320

IDD3P-F

-4A

280

mA

Fast PDN Exit

MRS(12) = 0

-5C

200

Active power-down

standby current

IDD3P-S

-4A

160

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address

bus inputs are STABLE;

Data bus inputs are

FLOATING

Slow PDN Exit

MRS(12) = 1

-5C

680

Active standby current

IDD3N

-4A

600

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operating)

(Another rank is in IDD2P)

IDD4R

-5C

-4A

1000

832

mA

Operating current

(Burst read operating)

(Another rank is in IDD3N)

IDD4R

-5C

-4A

1300

1100

mA

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write operating)

(Another rank is in IDD2P)

IDD4W

-5C

-4A

1000

832

mA

Operating current

(Burst write operating)

(Another rank is in IDD3N)

IDD4W

-5C

-4A

1300

1100

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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