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EBE52UD6AFSA-5C-E Datasheet(PDF) 6 Page - Elpida Memory |
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EBE52UD6AFSA-5C-E Datasheet(HTML) 6 Page - Elpida Memory |
6 / 23 page EBE52UD6AFSA Data Sheet E0722E30 (Ver. 3.0) 6 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 25 Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H 5.0ns* 1 26 Maximum data access time (tAC) from clock at CL = 3 0 1 1 0 0 0 0 0 60H 0.6ns* 1 27 Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH 15ns 28 Minimum row active to row active delay (tRRD) 0 0 1 0 1 0 0 0 28H 10ns 29 Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH 15ns 30 Minimum active to precharge time (tRAS) 0 0 1 0 1 1 0 1 2DH 45ns 31 Module rank density 0 1 0 0 0 0 0 0 40H 256M bytes 32 Address and command setup time before clock (tIS) -6E 0 0 1 0 0 0 0 0 20H 0.20ns* 1 -5C 0 0 1 0 0 1 0 1 25H 0.25ns* 1 -4A 0 0 1 1 0 1 0 1 35H 0.35ns* 1 33 Address and command hold time after clock (tIH) -6E 0 0 1 0 1 0 0 0 28H 0.28ns* 1 -5C 0 0 1 1 1 0 0 0 38H 0.38ns* 1 -4A 0 1 0 0 1 0 0 0 48H 0.48ns* 1 34 Data input setup time before clock (tDS) -6E, -5C 0 0 0 1 0 0 0 0 10H 0.10ns* 1 -4A 0 0 0 1 0 1 0 1 15H 0.15ns* 1 35 Data input hold time after clock (tDH) -6E 0 0 0 1 1 0 0 0 18H 0.18ns* 1 -5C 0 0 1 0 0 0 1 1 23H 0.23ns* 1 -4A 0 0 1 0 1 0 0 0 28H 0.28ns* 1 36 Write recovery time (tWR) 0 0 1 1 1 1 0 0 3CH 15ns* 1 37 Internal write to read command delay (tWTR) -6E, -5C 0 0 0 1 1 1 1 0 1EH 7.5ns* 1 -4A 0 0 1 0 1 0 0 0 28H 10ns* 1 38 Internal read to precharge command delay (tRTP) 0 0 0 1 1 1 1 0 1EH 7.5ns* 1 39 Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H TBD 40 Extension of Byte 41 and 42 0 0 0 0 0 0 0 0 00H Undefined 41 Active command period (tRC) 0 0 1 1 1 1 0 0 3CH 60ns* 1 42 Auto refresh to active/ Auto refresh command cycle (tRFC) 0 1 1 0 1 0 0 1 69H 105ns* 1 43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H 8ns* 1 44 Dout to DQS skew -6E 0 0 0 1 1 0 0 0 18H 0.24ns* 1 -5C 0 0 0 1 1 1 1 0 1EH 0.30ns* 1 -4A 0 0 1 0 0 0 1 1 23H 0.35ns* 1 |
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