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EDD1216AATA-5C-E Datasheet(PDF) 7 Page - Elpida Memory |
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EDD1216AATA-5C-E Datasheet(HTML) 7 Page - Elpida Memory |
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7 / 48 page  EDD1216AATA-5 Data Sheet E0443E40 (Ver. 4.0) 7 -5B -5C Parameter Symbol min. max. min. max. Unit Notes Mode register set command cycle time tMRD 2 — 2 — tCK Active to Precharge command period tRAS 40 120000 40 120000 ns Active to Active/Auto refresh command period tRC 55 — 60 — ns Auto refresh to Active/Auto refresh command period tRFC 70 — 70 — ns Active to Read/Write delay tRCD 15 — 18 — ns Precharge to active command period tRP 15 — 18 — ns Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — ns Active to active command period tRRD 10 — 10 — ns Write recovery time tWR 15 — 15 — ns Auto precharge write recovery and precharge time tDAL (tWR/tCK)+ (tRP/tCK) — (tWR/tCK)+ (tRP/tCK) — tCK 13 Internal write to Read command delay tWTR 2 — 2 — tCK Average periodic refresh interval tREF — 15.6 — 15.6 µs Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see ‘Timing Waveforms’ section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns, tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4) tDAL = 7 clocks |
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