EDD5104ADTA-7B datasheet(5/49 Pages) ELPIDA

Part #	EDD5104ADTA-7B

Description	512M bits DDR SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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5 / 49 page

EDD5104ADTA, EDD5108ADTA, EDD5116ADTA

Data Sheet E0384E30 (Ver. 3.0)

5

DC Characteristics 1 (TA = 0 to +70

°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

max.

Parameter

Symbol

Grade

× 4

× 8

× 16

Unit

Test condition

Notes

Operating current (ACT-

PRE)

IDD0

-6B

-7A, -7B

150

135

150

135

150

135

mA

CKE ≥ VIH,

tRC = tRC (min.)

1, 2, 9

Operating current

(ACT-READ-PRE)

IDD1

-6B

-7A, -7B

190

170

200

175

210

180

mA

CKE ≥ VIH, BL = 4,

CL = 2.5,

tRC = tRC (min.)

1, 2, 5

Idle power down standby

current

IDD2P

3

mA

CKE ≤ VIL

4

Floating idle standby

current

IDD2F

-6B

-7A, -7B

30

25

30

25

30

25

mA

CKE ≥ VIH, /CS ≥ VIH,

DQ, DQS, DM = VREF

4, 5

Quiet idle standby current IDD2Q

20

mA

CKE ≥ VIH, /CS ≥ VIH,

DQ, DQS, DM = VREF

4, 10

Active power down

standby current

IDD3P

20

mA

CKE ≤ VIL

3

Active standby current

IDD3N

-6B

-7A, -7B

65

55

65

55

65

55

mA

CKE ≥ VIH, /CS ≥ VIH

tRAS = tRAS (max.)

3, 5, 6

Operating current

(Burst read operation)

IDD4R

-6B

-7A, -7B

230

200

250

210

270

230

mA

CKE ≥ VIH, BL = 2,

CL = 2.5

1, 2, 5, 6

Operating current

(Burst write operation)

IDD4W

-6B

-7A, -7B

230

200

250

210

270

230

mA

CKE ≥ VIH, BL = 2,

CL = 2.5

1, 2, 5, 6

Auto Refresh current

IDD5

-6B

-7A, -7B

320

300

320

300

320

300

mA

tRFC = tRFC (min.),

Input ≤ VIL or ≥ VIH

Self refresh current

IDD6

4

mA

Input ≥ VDD – 0.2 V

Input ≤ 0.2 V

Self refresh current

((L-version))

IDD6

-xxL

3

mA

Operating current

(4 banks interleaving)

IDD7A

-6B

-7A, -7B

490

410

510

430

530

450

mA

BL = 4

1, 5, 6, 7

Notes: 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one clock cycle.

6. DQ, DM and DQS transition twice per one clock cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once every two clock cycles.

10. Command/Address stable at ≥ VIH or ≤ VIL.

DC Characteristics 2 (TA = 0 to +70

°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

Parameter

Symbol

min.

max.

Unit

Test condition

Notes

Input leakage current

ILI

–2

2

µA

VDD ≥ VIN ≥ VSS

Output leakage current

ILO

–5

5

µA

VDDQ ≥ VOUT ≥ VSS

Output high current

IOH

–15.2

—

mA

VOUT = 1.95V

Output low current

IOL

15.2

—

mA

VOUT = 0.35V

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