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EDE5104AGSE-6C-E Datasheet(PDF) 1 Page - Elpida Memory |
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EDE5104AGSE-6C-E Datasheet(HTML) 1 Page - Elpida Memory |
1 / 65 page Document No. E0715E20 (Ver. 2.0) Date Published July 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2005 PRELIMINARY DATA SHEET 512M bits DDR2 SDRAM EDE5104AGSE (128M words × 4 bits) EDE5108AGSE (64M words × 8 bits) Description The EDE5104AGSE is a 512M bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDE5108AGSE is a 512M bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 4 banks. They are packaged in 60-ball FBGA ( µBGA) package. Features • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: center- aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data mask (DM) for write data • Burst lengths: 4, 8 • /CAS Latency (CL): 3, 4, 5 • Auto precharge operation for each burst access • Auto refresh and self refresh modes • Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • SSTL_18 compatible I/O • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation. • FBGA (µBGA) package with lead free solder (Sn-Ag-Cu) RoHS compliant |
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