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EDS6416AHTA-TI Datasheet(PDF) 1 Page - Elpida Memory |
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EDS6416AHTA-TI Datasheet(HTML) 1 Page - Elpida Memory |
1 / 49 page Document No. E0636E10 (Ver. 1.0) Date Published January 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2005 PRELIMINARY DATA SHEET 64M bits SDRAM WTR (Wide Temperature Range) EDS6416AHTA-TI (4M words × 16 bits) Description The EDS6416AHTA is a 64M bits SDRAMs organized as 1,048,576 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 54-pin plastic TSOP (II). Features • 3.3V power supply • Clock frequency: 133MHz (max.) • Single pulsed /RAS • ×16 organization • 4 banks can operate simultaneously and independently • Burst read/write operation and burst read/single write operation capability • 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8, full page) Interleave (BL = 1, 2, 4, 8) • Programmable /CAS latency (CL): 2, 3 • Byte control by UDQM and LDQM • Refresh cycles: 4096 refresh cycles/64ms • 2 variations of refresh Auto refresh Self refresh • TSOP (II) package with lead free solder (Sn-Bi) • Wide temperature range Ambient temperature range: –40 to +85°C Pin Configurations /xxx indicate active low signal. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 A3 VDD 54-pin Plastic TSOP (II) (Top view) Address input Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable A0 to A11 BA0, BA1 DQ0 to DQ15 /CS /RAS /CAS /WE Input/output mask Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection LDQM, UDQM CKE CLK VDD VSS VDDQ VSSQ NC |
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