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EDX5116ABSE-3A-E Datasheet(PDF) 7 Page - Elpida Memory |
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EDX5116ABSE-3A-E Datasheet(HTML) 7 Page - Elpida Memory |
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7 / 78 page  Preliminary Data Sheet E0643E30 (Ver. 3.0) 7 EDX5116ABSE Pin Description Table 1 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These include VDD and GND for the core and inter- face logic, VREF for receiving input signals, and VTERM for driving output signals. The next group of pins are used for high bandwidth memory accesses. These include DQ15..0 and DQN15..0 for carrying read and write data signals, RQ11..0 for carrying request sig- nals, and CFM and CFMN for carrying timing information used by the DQ, DQN, and RQ signals. The final set of pins comprise the serial interface that is used for control register accesses. These include RST for initializing the state of the device, CMD for carrying command signals, SDI, and SDO for carrying register read data, and SCK for car- rying the timing information used by the RST, SDI, SDO, and CMD signals. Table 1 Pin Description Signal I/O Type No. of pins Description VDD - - 22 Supply voltage for the core and interface logic of the device. GND - - 24 Ground reference for the core and interface logic of the device. VREF - - 1 Logic threshold reference voltage for RSL signals. VTERM - - 4 Termination voltage for DRSL signals. DQ15..0 I/O DRSLa 16 Positive data signals that carry write or read data to and from the device. DQN15..0 I/O DRSLa 16 Negative data signals that carry write or read data to and from the device. RQ11..0 I RSLa 12 Request signals that carry control and address information to the device. CFM I DIFFCLKa 1 Clock from master — Positive interface clock used for receiving RSL signals, and receiving and transmitting DRSL signals from the Channel. CFMN I DIFFCLKa 1 Clock from master — Negative interface clock used for receiving RSL signals, and receiving and transmitting DRSL signals from the Channel. RST I RSLa 1 Reset input — This pin is used to initialize the device. CMD I RSLa 1 Command input — This pin carries command, address, and control register write data into the device. SCK I RSLa 1 Serial clock input — Clock source used for reading from and writing to the con- trol registers. SDI I RSLa 1 Serial data input — This pin carries control register read data through the device. This pin is also used to initialize the device. SDO O CMOSa 1 Serial data output — This pin carries control register read data from the device. This pin is also used to initialize the device. RSRV - - 2 Reserved pins — Follow Rambus XDR system design guidelines for connecting RSRV pins Total pin count per package 104 a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1. All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1. |
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