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EDX5116ABSE-2A-E Datasheet(PDF) 3 Page - Elpida Memory |
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EDX5116ABSE-2A-E Datasheet(HTML) 3 Page - Elpida Memory |
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3 / 78 page  Preliminary Data Sheet E0643E30 (Ver. 3.0) 3 EDX5116ABSE General Description The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a signal name denotes the complemen- tary signal of a differential pair. A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit- windows on each signal, while the DQ bus uses a set of 16 bit- windows on each signal. In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) com- mand. This causes row Ra of bank Ba in the memory compo- nent to be loaded into the sense amp array for the bank. A second request packet at clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command. This causes the data packet D(a2) at edge T6 to be also written to column Ca2. A final request packet at clock edge T14 contains a precharge (PRE) command. The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD -W, tCC , and tWRP . In addition, the spacing between the request packets and data packets are constrained by the tCWD parameter. The spacing of the CFM/CFMN clock edges is constrained by tCYCLE. Figure 1 XDR DRAM Device Write and Read Transactions The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command. This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final request packet at clock edge T10 contains a PRE command. The spac- ings between the request packets are constrained by the follow- ing timing parameters in the diagram: tRCD -R, tCC , and tRDP . In addition, the spacing between the request and data packets are constrained by the tCAC parameter. T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T8 Transaction a: WR a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCWD tCYCLE tWRP tRCD-W a1 WR a2 WR a3 PRE a0 ACT D(a2) D(a1) Write Transaction DQ15..0 DQN15..0 CFM CFMN RQ11..0 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T8 Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCAC tCYCLE tRDP tRCD-R a1 RD a2 RD a3 PRE a0 ACT Q(a2) Q(a1) Read Transaction DQ15..0 DQN15..0 CFM CFMN RQ11..0 |
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